1. Field of the Invention
The present invention relates to a voltage regulator which is excellent in responsiveness with low power consumption.
2. Description of the Related Art
FIG. 3 shows a circuit diagram of a conventional voltage regulator. A reference voltage circuit 20 outputs a reference voltage Vref. A feedback voltage VFB which is obtained by dividing an output voltage Vout at an output terminal through a resistor 50 and a resistor 60 is outputted from a node between the resistor 50 and the resistor 60. A voltage amplifying circuit 30 controls a PMOS transistor 40 based on results of comparison between the feedback voltage VFB and the reference voltage Vref so that the output voltage Vout becomes constant (refer to JP 2001-282371 A for example).
However, in such a conventional voltage regulator, in order to obtain the stable output voltage Vout against power supply fluctuation, it is necessary to increase a current consumed in the voltage amplifying circuit 30, and thus a large current is usually caused to flow through the voltage amplifying circuit 30 irrespective of a fluctuation level in a power supply voltage.